In general, an image sensor is a semiconductor device for converting optical images into electric signals, and is typically classified as a charge coupled device (CCD) or a CMOS image sensor.
The CCD has a plurality of photodiodes (PDs), which are arranged in the form of a matrix in order to convert optical signals into electric signals. The CCD includes a plurality of vertical charge coupled devices (VCCDs) provided between photodiodes and vertically arranged in the matrix so as to transmit electric charges in the vertical direction when the electric charges are generated from each photodiode; a plurality of horizontal charge coupled devices (HCCDs) for transmitting in the horizontal direction the electric charges that have been transmitted from the VCCDs; and a sense amplifier for outputting electric signals by sensing the electric charges being transmitted in the horizontal direction.
However, such a CCD has various disadvantages, such as a complicated drive mode, high power consumption, and so forth. Also, the CDD requires multi-step photo processes, so the manufacturing process for the CCD is complicated.
In addition, since it is difficult to integrate a controller, a signal processor, and an analog/digital converter (A/D converter) onto a single chip of the CCD, the CCD is unsuitable for compact-size products.
Recently, the CMOS image sensor has been spotlighted as a next-generation image sensor capable of solving the problem of the CCD.
The CMOS image sensor is a device employing a switching mode to sequentially detect an output of each unit pixel by means of MOS transistors using peripheral devices such as a controller and a signal processor, in which the MOS transistors are formed on a semiconductor substrate corresponding to the unit pixels through a CMOS technology.
That is, the CMOS sensor includes a PD and a MOS transistor in each unit pixel, and sequentially detects the electric signals of each unit pixel through the MOS transistor in a switching mode.
The CMOS image sensors are classified into 3T type, 4T type, and 5T type CMOS image sensors according to the number of transistors included in each pixel. The 4T type CMOS image sensor includes one PD and four transistors.
FIG. 1 is a circuit diagram showing a unit pixel of the conventional CMOS image sensor including a PD, which is a photodetector, and four n-channel metal-oxide semiconductor (NMOS) transistors.
As shown in FIG. 1, from among four NMOS transistors, a transfer transistor Tx transmits optical charges from the PD to the floating diffusion (FD).
A reset transistor Rx transmits a signal for resetting the FD to the level of a supply voltage VDD, a drive transistor Dx serves as a source follower, and a select transistor Sx receives a pixel data enable signal so as to transmit a pixel data signal.
Hereinafter, the operation of the CMOS image sensor having the above structure will be described.
First, the reset transistor Rx, the transfer transistor Tx, and the select transistor Sx are turned on so as to reset a unit pixel. At this time, depletion of the PD occurs, so that carrier charging is generated. The FD is charged with carriers to a level of the supply voltage VDD.
Next, the transfer transistor Tx is turned off, the select transistor Sx is turned on, and then the reset transistor Rx is turned off.
In this state, a controller reads out an output voltage V1 from the output terminal Out of the unit pixel and stores the output voltage V1 in a buffer. Then, the controller turns on the transfer transistor Tx so as to shift carriers of a capacitor Cp, which is changed according to intensity of light, into a capacitor Cf. After that, the controller reads out an output voltage V2 from the output terminal Out of the unit pixel and converts analog data for the output voltages V1 and V2 into digital data, thereby completing one operational period of the unit pixel.
FIGS. 2 to 6 are views showing a method for manufacturing the conventional CMOS image sensor.
As shown in FIG. 2, a low-density P− type epitaxial layer 62 is formed on a high-density P++ type semiconductor substrate 61 by performing an epitaxial process.
Then, an active area and an isolation area are defined on the semiconductor substrate 61, and an isolation layer 63 is formed on the isolation area through a shallow trench isolation (STI) process.
A gate insulating layer 64 and a conductive layer are sequentially deposited on the entire surface of the epitaxial layer 62 formed with the isolation layer 63, and the conductive layer and the gate insulating layer 64 are selectively removed, thereby forming a gate electrode 65.
As shown in FIG. 3, a first photoresist film 66 is coated on the entire surface of the semiconductor substrate 61, and then an exposure and development process is performed with respect to the photoresist film such that blue, green, and red PD areas can be exposed.
Thereafter, low-density N− type dopants are implanted into the epitaxial layer 62 by using the first photoresist film 66 as a mask, thereby forming an N− type diffusion area 67.
Then, as shown in FIG. 4, after completely removing the first photoresist film 66 and depositing an insulating layer on the entire surface of the semiconductor substrate 61, insulating sidewalls 68 are formed at both sides of the gate electrode 65 by performing an etch-back process.
Next, a second photoresist film 69 is coated on the entire surface of the semiconductor substrate 61, and an exposure and development process is performed with respect to the second photoresist film 69 such that a source/drain area of the transistors can be exposed while covering the PD areas.
Thereafter, high-density N+ type dopants are implanted into the exposed source/drain area by using the second photoresist film 69 as a mask, thereby forming an N+ type diffusion area (i.e., an FD area) 70.
Then, as shown in FIG. 5, after removing the second photoresist film 69, a third photoresist film 71 is coated on the entire surface of the semiconductor substrate 61, and then the exposure and development process is performed with respect to the third photoresist film 71 such that the PD areas can be exposed.
Next, P type dopants are implanted into the PD areas formed with the N− type diffusion area 67 by using the third photoresist film 71 as a mask, thereby forming a Po type diffusion area 72 on the surface of the semiconductor substrate.
Then, as shown in FIG. 6, the third photoresist film 71 is removed, and a heat treatment process is performed with respect to the semiconductor substrate 61, thereby diffusing the dopant diffusion areas.
However, in the conventional CMOS image sensor, since the voltage variation increases as capacitance of the FD area reduces under the same number of electrons, it is difficult to reduce the node capacitance of the FD area.
In addition, since the voltage variation derived from electrons exclusively generated from the PD area due to an optical energy is reduced as the node capacitance of the FD area is increased, the overall sensitivity of the image sensor may be degraded.